A semiconductor device in JP-A-2000-260984 is shown as a related art in FIG. 42. The semiconductor device 1 includes: an n+ type (first conductivity type) drain region 2; an n type (first conductivity type) drift region 6 connecting with the n+ type drain region 2; a p type (second conductivity type) body region 12; an n+ type source region 14 connecting with the p type body region 12; a gate electrode 20 filled with being covered by an insulation film 18 in a gate trench 13 that penetrates the p type body region 12; a p type silicon region (semiconductor region) 8 adjoining the n type drift region 6; and an n− type (first conductivity type) silicon region 11 covering the n type drift region 6 and the p type silicon region 8. It further includes a p type silicon region 22 connecting a rear portion of the p type body region 12 and an upper and rear portion of the p type silicon region 8. The n type drift region 6 and the p type silicon region 8 form alternate layers that are orthogonal to the surface of the drain region. The alternate layers constitute super-junction structure 4.
Applying positive electric voltage to the gate electrode 20 in the semiconductor device 1 leads to forming an n type channel 12a in the p type body region 12. A carrier (electron) thereby flows from the n+ type source region 14 through the n type channel 12a in the p type body region 12 and the n type drift region 6 to the n+ type drain region 2.
Connecting the gate electrode 20 to ground results in canceling the channel 12a from the p type body region 12. The semiconductor 1 is thereby turned off. In the semiconductor device 1, depletion layers are widened towards the n type drift region 6 and the p type silicon region 8 from a pn junction 7 between the n type drift region 6 and the p type silicon region 8. The n type drift region 6 and the p type silicon region 8 are completely occupied with the depletion layers, so that withstanding voltage (break-down voltage) between the n+ type source region 14 and the n+ type drain region 2 is attained.
Conventional power MOS structure (not shown) does not include a super-junction structure 4. Withstanding voltage is therefore determined by depletion layers extended from a pn junction between the n type drift region and a p type body region. Typically, impurity concentration is lowered in the n type drift region in comparison with the p type body region, so that the n type drift region is completely occupied with the depletion layer. Required withstanding voltage is thereby attained.
When the drift region is formed of the super-junction structure 4 as shown in FIG. 42, the depletion layers extend towards the n type drift region 6 from the pn junctions 7 that are located in both sides of the drift region 6. To attain a certain withstanding voltage, a semiconductor device with the super-junction structure 4 can include a more impurity in the n type drift region 6 than a semiconductor without the super-junction structure 4. This results in obtaining a low ON-resistance semiconductor device with having the same certain withstand voltage.
In manufacturing a semiconductor device, a mask for forming the gate trench 13 may shift horizontally (in parallel with the surface of the drain region 2), or etching for forming the gate trench 13 may be practiced more deeply (orthogonally to the surface of the drain region 2) than a required depth. These manufacturing problems arise even at the present day when micro-fabrication is much progressed. In this case, without forming the n− type silicon region 11, the trench may reach the n type drift region 6 or the p type silicon region 8 through a bottom of the p type body region 12. Here, the carrier that passes through the n type channel in the p type body region forms a channel also in the p type silicon region 8 due to MOS effect before reaching the n type drift region 6. Channel resistance in the p type silicon region 8 is thereby increased, so that the ON resistance of the semiconductor device 1 is increased.
In the above semiconductor device 1, disposing the n− type silicon region covering the n type drift region 6 and the p type silicon region 8 prevents the ON resistance from increasing due to the manufacturing problems.
However, when the n− type silicon region 11 thoroughly isolates the p type silicon region 8 from the p type body region 12, the p type silicon region 8 is in floating electric potential. In this condition, when, during withstanding voltage, positive voltage is applied to the n+ type drain region 2 and the n+ type source region is connected to ground, voltage for extending the depletion layers towards the n type drift region 6 and the p type silicon region 8 may not be sufficiently applied to the pn junction between them. A characteristic of withstanding voltage may thereby become unstable. For preventing the p type silicon region 8 from remaining in the floating electric potential, the p type silicon region 22 is provided in a rear portion of the semiconductor device 1. It is for connecting an upper rear portion of the p type silicon region 8 and a rear portion of the p type body region 12 as shown in FIG. 42.
Here, the p type body region 12 and the p type silicon region 8 must be electrically connected through the silicon region 22 via a long electric current passage. During withstanding voltage, a virtual pnp transistor is formed among the p type body region 12, the n− type silicon region 11, and the p type silicon region 8. This pnp transistor sometimes shifts to an ON state due to voltage drop deriving from the long electric current passage. As a result, during withstanding voltage, a leak current may flow from the p type silicon region 8 through the n− type silicon region 11 to the p type body region 12.